In serial data communication, the channel through which information is transmitted (e.g., chip-to-chip or backplane interconnects,) imposes a limit on the bandwidth capacity, or rate at which information may pass through the channel. One significant limitation on achievable bandwidth is known as inter-symbol interference (ISI), which occurs when a portion of a signal representative of one bit of information interferes with a different portion of the signal representative of a different bit of information.
To overcome bandwidth limited chip-to-chip and backplane interconnects at high data rates, conventional high-speed transceivers implement a combination of a Decision Feedback Equalizer (DFE) on the Receiver (RX) side as well as a Feed Forward Equalization (FFE) on the Transmitter (TX) side. Although RX DFE has advantages such as not amplifying noise, it has a very strict timing constraint of one unit interval (UI) for the feedback path. Given the current transceiver data rates, one UI can be as small as 35.7 pico seconds (ps), which is very difficult to meet, even for cutting edge manufacturing processes.
For example, FIG. 1A illustrates a conventional architecture of a quarter-rate equalizer 100 comprising DFE samplers 031-034 for sampling/determining the value of an incoming signal based on the current integration performed by main taps 011-014 and DFE taps 021-024. The DFE taps 021-024 are constrained to integrate the current of signals from various DFE samplers 031-034 within one UI from when the sampler inputs become available.
A few techniques have been adopted in the industry to mitigate this timing constraint. For example, time-interleaving techniques such as half-rate or quarter-rate architecture can relax the DFE timing constraint for the second DFE tap and onward, but the DFE first tap timing constraint remains at one UI. Although loop unrolling can eliminate the analog settling time from the one UI timing constraint, loop unrolling adds incurs additional hardware resources, and also results in more power dissipation.
Recent transceiver designs use FFE in the TX side to equalize part of the channel losses. There are several drawbacks of putting FFE on the TX side. The first significant impact is related to the limit on the amplitude of the transmitted signal on the TX side. This limitation on the amplitude implies that, when equalization is used, the total energy sent from the TX to the far end receiver (RX) is reduced.
Conventional architectures implement back-channel communication between the RX and TX as a way to tune the TX FFE coefficients following the RX requests. Back-channel communication costs extra hardware. Additionally, it can be difficult to find a combined optimal solution for FFE and DFE, given a long feedback latency of the back-channel, as well as the limited resolution of the far-end TX. Moreover, after channel attenuation and reflection, TX FFE becomes less effective as compared to directly applying FFE in the far end RX. Given these and other disadvantages, putting FFE on the RX side is becoming more popular.
The impact of pre-cursor ISI on receiver performance becomes significant for interconnects operating at 10 Gbps and above. The higher the link speed, the higher the potential impact of the pre cursor ISI on the recovered eye diagram. An eye diagram is generated by superimposing a stream of pulses of “0's” and “1's.” Ideally, an eye diagram has a rectangular shape because the “0's” and “1's” pulses have perfect edges (i.e., zero rise and fall time). Due to ISI, the received pulses become imperfect, and the resulting diagram looks more like an “eye.” As ISI increases, the eye diagram looks more and more like a closed/narrower eye. Received signals having a closed-eye characteristic are less effective in driving the FFE filter, resulting in an equalizer having little benefit.
Unlike DFE, which can only equalize post cursors of impulse response, FFE is able to equalize pre cursors as well. Conventional architectures of RX FFE require analog elements (such as inductors and capacitors) in order to create a one UI distance between taps. These analog elements typically occupy a large area and are difficult to integrate into a System-on-Chip (SOC). Furthermore, at very high speeds, the insertion loss is significant, leading to a closed eye diagram at the receiver pads even, after a Continuous Time Linear Equalizer (CTLE) has been applied to the input signal.
More recently, some equalizers implement FFE filters by feed forwarding the input signal held at the SNH directly to the current integration logic. Such conventional architectures also result in a closed eye at the receiver at high data rates because the insertion loss is significant at high speeds. For example, the quarter-rate equalizer 101 of FIG. 1B consists of pre/post cursor taps 131-134 for integrating the current of the outputs of sample and hold (SNH) 121-124. As used herein, current integration refers to the process of summing/adding current onto a capacitive load. As illustrated, SNH 121-124 outputs are based on un-equalized outputs of SNH 101-104. Thus, the performance of pre/post cursor taps 131-134 is reduced because they integrate based on un-equalized signals, resulting in a closed eye at the receiver at high data rates.